Continuous scaling of silicon-based metal oxide semiconductor field effect transistors (MOSFETs) has contributed to relentless advances in semiconductor technology. As the device scale approaches nanometer ranges, further scaling of semiconductor devices faces various challenges. In light of this, many methods of improving device performance without resorting to scaling have recently been explored.
One widely adopted approach for improving performance of semiconductor devices without relying on scaling is to increase carrier (electron or hole) mobility in a MOSFET. When stress is applied to the channel of a semiconductor transistor, the mobility of carriers, and as a consequence, the transconductance and the on-current of the transistor are altered from their original values for an unstressed semiconductor. This is because the applied stress and the resulting strain on the semiconductor structure within the channel affects the band gap structure (i.e., breaks the degeneracy of the band structure) and changes the effective mass of carriers. The effect of the stress depends on the crystallographic orientation of the plane of the channel, the direction of the channel within the crystallographic orientation, and the direction of the applied stress. Manipulating stress is an effective way of improving the minority carrier mobility in a MOSFET and increasing the transconductance (or reduced serial resistance) of the MOSFET that requires relatively small modifications to semiconductor processing while providing significant enhancement to MOSFET performance.
The effect of uniaxial stress, i.e., a stress applied along one crystallographic direction, on the performance of semiconductor devices, especially on the performance of MOSFET (or a “FET” in short) devices built on a silicon substrate, has been extensively studied in the semiconductor industry. For a PMOSFET (or a “PFET” in short) utilizing a silicon channel, the mobility of minority carriers in the channel (which are holes in this case) increases under uniaxial compressive stress along the direction of the channel, i.e., the direction of the movement of holes or the direction connecting the drain to the source. Conversely, for an NMOSFET (or an “NFET” in short) devices utilizing a silicon channel, the mobility of minority carriers in the channel (which are electrons in this case) increases under uniaxial tensile stress along the direction of the channel, i.e., the direction of the movement of electrons or the direction connecting the drain to the source. These opposite requirements for the type of stress for enhancing carrier mobility between the PMOSFETs and NMOSFETs have led to prior art methods for applying at least two different types of stress to the semiconductor devices on the same integrated chip.
Different methods of “stress engineering,” or “strain engineering” as it is alternatively called, on the channel of a MOSFET have been known in the prior art. One group of methods creates a “global stress,” that is, a stress applied to a general transistor device region generated from the substrate. A global stress is generated by such structures as SiGe stress relaxed buffer layers, Si:C stress relaxed buffer layers, or silicon germanium structures on an insulator.
Another group of methods generates a “local stress,” that is, a stress applied only to local areas adjacent to the channel from a local structure. A local stress is generated by such structures as stress liners, embedded SiGe source/drain structures, embedded Si:C source/drain structures, stress-generating shallow trench isolation structures, and stress-generating silicides. An increase in the on-current of up to 50% and an overall chip speed increase up to 40% have been reported on semiconductor devices utilizing these methods.
One of the most common methods of applying a local stress is the use of stress liners. Since each stress liner has a certain stress level either compressive or tensile, two separate stress liners, commonly called “dual stress liners,” are used to separately create a tensile stress and a compressive stress in two different regions of the same integrated circuit. An exemplary method for forming two separate liners is disclosed in U.S. Patent Application Publication No. 2005/0093030 A1 to Doris et al., which discloses the use of two separate liners such that an NFET area is covered with a tensile liner that directly overlies underlying NFETs, an optional dielectric layer, and a compressive liner while a PFET area is covered only with the compressive liner, The liner stack over the NFET area applies tensile stress to the underlying NFETs and the compressive liner over the PFET area applies compressive stress to the underlying PFETs so that both PFETs and NFETs have enhanced performance through stress engineering.
Referring to FIG. 1, an exemplary dual stress liner structure according to the prior art is shown. A first MOSFET 100 of one conductivity type and a second MOSFET 200 of the opposite conductivity type, i.e., a pair of a p-type MOSFET and an n-type MOSFET, are formed on a semiconductor substrate 18. The first MOSFET 100 comprises a portion of the substrate layer 22, a gate dielectric 30, a gate conductor 38 which comprises a gate polysilicon 32 and a gate silicide 36, a spacer 34, source and drain regions 40, a source and drain silicide 42, a first stress liner 50, and an etch stop layer 52. Similarly, the second MOSFET 200 comprises another portion of the substrate 22, a gate dielectric 30, a gate conductor 38 which comprises a gate polysilicon 32 and a gate silicide 36, a spacer 34, source and drain regions 40, a source and drain silicide 42, and a second stress liner 70. Shallow trench isolation (STI) 24 provides electrical isolation between the first MOSFET 100 and the second MOSFET 200. Typically, boundary region 72 between the first stress liner 50 and the second stress liner 70 comprises a region where first and second stress liners overlap, However, alternative boundary region geometries are possible. For example, boundary region 72 might comprise a small gap between first and second stress liners instead of an overlap region.
The first stress liner 50 applies a first stress to the first MOSFET 100 and the second stress liner 70 applies a second stress to the second MOSFET 200. The first stress and the second stress are different, and typically, the two stresses are opposite in nature, i.e., one is compressive and the other is tensile. Further, the substrate is typically a silicon substrate and a compressive stress is applied to a p-type MOSFET (PMOSFET, or a “PFET”) and a tensile stress is applied to an n-type MOSFET (NMOSFET, or an “NFET”). The first MOSFET 100 may be a PMOSFET with a compressive stress or an NMOSFET with a tensile stress depending on the method of fabrication. A MOSFET of the opposite polarity with the opposite type of stress is selected for the second MOSFET 200 relative to the first MOSFET 100.
The effect of a stress on conductivity of a material is called the “piezoresistance effect.” Semiconductor materials typically display a piezoresistive effect since the stress induces strain, which in turn changes the band structure of the semiconductor material. The piezoresistance effect depends on the semiconductor material, doping type of the semiconductor materal, direction of the current flow relative to the crystallographic axes of the semiconductor material, direction and magnitude of the applied stress, and the temperature of the semiconductor material. Quantitative analysis of the piezoresistance effect on silicon is disclosed in Y. Kanda, “A Graphical Representation of the Piezoresistance Coefficients in Silicon,” IEEE Transactions on Electron Devices, Vol. ED-29, pp. 64-70, No. 1, Jan. (1982), which is herein incorporated by reference.
Piezoresistive coefficients are defined as a fractional change in the resistance of a semiconductor material per unit pressure. A longitudinal piezoresistive coefficient is a measure of fractional change in the resistance per applied tensile stress in the direction of current flow (i.e., in the direction of the channel, in the case of field effect transistors). A transverse piezoresistive coefficient is a measure of fractional change in the resistance per applied tensile stress in the direction perpendicular to the current flow and within the plane of the channel (i.e., in the direction of the gate line, in the case of field effect transistors). While estimation of piezoresistive coefficients π in a PFET in the on-state is difficult since holes are predominant charge carriers in the inversion layer comprising n-doped silicon instead of electrons, the piezoresistive coefficients π may be estimated from p-doped silicon which contains holes as charge carriers in a normal state, i.e., in the absence of an inversion condition. Positive correlation between piezoresistive coefficients of an inversion layer formed in an n-doped silicon layer and piezoresistive coefficients of a p-doped silicon layer in a normal state is known. Similar correlation holds between piezoresistive coefficients of an inversion layer formed in a p-doped silicon layer and piezoresistive coefficients of an n-doped silicon layer in a normal state.
Typical silicon-based semiconductor devices employ a substrate containing a silicon layer having a (001) surface orientation. Referring to FIG. 2, a typical orientation of a p-type field effect transistor (PFET) formed in a silicon layer having a (001) surface orientation is shown, in which the current flow direction, i.e., the direction of a channel, is along the [110] crystallographic direction, and the direction of a gate line is along the [1 1 0] crystallographic direction. The longitudinal piezoelectric coefficient, as estimated from an equivalent p-doped silicon layer, is on the order of 71.8×10−12 cm2/dyne and the lateral transverse piezoelectric coefficient estimated in the same manner is on the order of −66.3×10−12 cm2/dyne. Thus, the resistivity of the channel containing n-doped silicon in an inversion state during the on-state of the PFET increases under a longitudinal tensile stress and decreases under a lateral transverse tensile stress. To enhance conductivity of the channel, and consequently the on-current of the PFET, a longitudinal compressive stress and/or a transverse tensile stress is required on the PFET.
While prior art structures advantageously employ piezoresistive effects of silicon to enhance performance of field effect transistors, there exists a need for semiconductor structures that can enhance performance of complementary metal oxide semiconductor (CMOS) transistors on a silicon substrate even further. In particular, a PFET structure that provides enhanced performance through constructive manipulation of piezoresistive effects is desired for high performance CMOS circuits.
Further, when multiple stress-generating structures are formed on a semiconductor substrate, the performance of a particular semiconductor device is affected by primary stress effects from stress-generating structures in the particular semiconductor device itself, as well as by secondary stress effects from stress-generating structures in adjacent devices. Therefore, there exists a need for a semiconductor structure that may advantageously employ secondary stress effects from neighboring semiconductor devices.